Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
US8933488B2 · kind B2 · utility
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4References
36Claims
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Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Dec 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.