Inventor · Palo Alto, CA, US

Aneesh Nainani

6Patents
2h-index
13Co-inventors
37Inventor score

Filing activity: Dec 1, 2011 → Nov 12, 2015

Most-cited inventions

PatentTitleAreaCited byStatus
US9570307B2 Methods of doping substrates with ALD Electricity 5 Active
US9378941B2 Interface treatment of semiconductor surfaces with high density low energy plasma Electricity 3 Active
US9218973B2 Methods of doping substrates with ALD Electricity 2 Active
US9543172B2 Apparatus for providing and directing heat energy in a process chamber Electricity 0 Active
US8933488B2 Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS Electricity 0 Active
US8969924B2 Transistor-based apparatuses, systems and methods Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.