System and method for variable frequency clock generation
US8933737B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 4, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Oct 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.