Means and method for operating a resistive array
US8934293B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2011 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Apr 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be manufactured as a monolithic integrated circuit at low cost by virtue of the limited number of steps per layer of memory elements. The low number of steps results by having the storage elements separated by a resistive component as opposed to an active component. The 3-D array is in essence, an array of 2-D resistive arrays (row-planes) having a long dimension (typically along the rows) and a short dimension (typically in the direction of the stacked layers). Any one row-plane can be isolated from the rest and be accessed independently from all of the other row-planes in the 3-D array. This makes it possible to operate and analyze a single row-plane as a mostly stand-alone circuit. The present invention lends itself to single bit accesses as well as simultaneous multiple bit accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.