Semiconductor memory devices having internal clock signals and memory systems including such memory devices
US8934317B2 · kind B2 · utility
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5References
18Claims
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Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Feb 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.