Signal receiver with multi-level sampling
US8934590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Dec 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.