Echo prevention circuit having signal subtracter feature
US8934621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2006 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/23
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An echo prevention circuit comprises an input terminal to which a first input signal is input; a first FIR filter into which the first input signal is input through the input terminal; a second FIR filter into which the first input signal is input at the same time as into the first FIR filter; an input/output terminal to which an output signal of the first FIR filter is output or a second input signal is input; a subtracter that subtracts an output signal of the second FIR filter from a combined signal of the output signal of the first FIR filter and the second input signal; and an output terminal to which an output signal of the subtracter is output. The first and the second FIR filters have such filter coefficients that the output signal through the output terminal has only the output signal from the first FIR filter removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.