Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor
US8935483B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.