Patent · US Active

Circuitry and method for multi-bit correction

US8935590B2 · kind B2 · utility

3Cited by

11References

45Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kern · Munich, DE
Michael Goessel · Roter Dudel, DE

Key dates

Filing date	Oct 31, 2012
Grant date	Jan 13, 2015
Priority date	—
Expiry date	Mar 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/1006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.