Patent · US Active

Instruction scheduling approach to improve processor performance

US8935685B2 · kind B2 · utility

1Cited by

7References

3Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Juergen Koehl · Holzgerlingen, DE
Jens Leenstra · Nagold, DE
Philipp Panitz · Eppelheim, DE
Hans Schlenker · Frankfurt, DE

Key dates

Filing date	Apr 28, 2012
Grant date	Jan 13, 2015
Priority date	—
Expiry date	Dec 12, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F2115/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.