Method for fabricating an integrated device
US8936960B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0742
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.