Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit

US8937494B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Andreas H. A. Arp · Nufringen, DE
• Guenther Hutzl · Sindelfingen, DE
• Michael V. Koch · Ehningen, DE
• Matthias Ringe · Lörrach, DE

Key dates

• Filing date: Dec 10, 2013
• Grant date: Jan 20, 2015
• Expiry date: Dec 10, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/1534
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for detecting rising and falling transitions of internal signals of an array or integrated circuit. An apparatus used in the method comprises a delay line with a plurality of first to Nth delay elements, latches, and first to Nth groups of logic gates. Each of the first to Nth groups of the logical gates includes an AND gate and a NOR gate. The method determines rising and falling signals based on output signals of the logic gates in the apparatus; in odd numbered groups of the logic gates, the AND gate detects the rising transition and the NOR gate detects the falling transition; in even numbered groups of the logic gates, the AND gate detects the falling transition and the NOR gate detects the rising transition.