Transparent processing core and L2 cache connection
US8938585B1 · kind B1 · utility
1Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2014 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Mar 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.