In-situ metal gate recess process for self-aligned contact application
US8940597B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.