Integrated circuit package and method for manufacturing the same
US8941225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jul 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package and a method for manufacturing the same are provided. The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.