Electronic chip and method of fabricating the same
US8941231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jul 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.