Patent · US Active

Using collapse limiter structures between elements to reduce solder bump bridging

US8941236B2 · kind B2 · utility

2Cited by

17References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ameya Limaye · Chandler, US
Richard J. Harries · Chandler, US
Sandeep B. Sane · Chandler, US

Key dates

Filing date	Sep 28, 2012
Grant date	Jan 27, 2015
Priority date	—
Expiry date	Sep 28, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface.Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.