Systems, memories, and methods for operating memory arrays
US8942054B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Jun 25, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Dec 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/783
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.