Protocol for memory power-mode control
US8942056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Feb 15, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.