Apparatus and methods for clock alignment for high speed interfaces
US8942333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jan 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.