System and method to implement a matrix multiply unit of a broadband processor
US8943119B2 · kind B2 · utility
27Cited by
47References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.