Method and apparatus for improving cache efficiency
US8943273B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2009 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Dec 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide methods for cache efficiency. A method for cache efficiency can include storing data in a buffer entry in association with a cache array in response to a first store instruction that hits the cache array before the first store instruction is committed. Further, when a dependent load instruction is subsequent to the first store instruction, the method can include providing the data from the buffer entry in response to the first dependent load instruction. When a second store instruction overlaps an address of the first store instruction, the method can include coalescing data of the second store instruction in the buffer entry before the second store instruction is committed. When the second store instruction is followed by a second dependent load instruction, the method can include providing the coalesced data from the buffer entry in response to the second dependent load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.