Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information
US8943300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2008 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.