Combo static flop with full test
US8943375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Aug 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.