Semiconductor device reliability model and methodologies for use thereof
US8943444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Jun 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.