Simulating scan tests with reduced resources
US8943457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | May 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.