Patent · US Active

Fabricating a wafer level semiconductor package having a pre-formed dielectric layer

US8945991B2 · kind B2 · utility

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Key dates

Filing dateNov 22, 2013
Grant dateFeb 3, 2015
Priority date—
Expiry dateNov 22, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/12042
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.