Semiconductor package with through silicon vias
US8946742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2010 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Dec 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.