Integrated MOS power transistor with thin gate oxide and low gate charge

US8946851B1 · kind B1 · utility

Assignee

• Maxim Integrated Products, Inc. · US

Inventors

• Joel M. McGregor · San Jose, US
• Vishnu Khemka · Phoenix, US

Key dates

• Filing date: Apr 13, 2012
• Grant date: Feb 3, 2015
• Expiry date: Sep 2, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.