Inventor · San Jose, CA, US

Joel M. McGregor

15Patents

5h-index

12Co-inventors

63Inventor score

Filing activity: Mar 13, 1997 → May 21, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US5811315A	Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure	Emerging Cross-Sectional Technologies	47	Expired
US6362064B1	Elimination of walkout in high voltage trench isolated devices	Electricity	24	Expired
US10090409B2	Method for fabricating LDMOS with self-aligned body	Electricity	10	Active
US8987818B1	Integrated MOS power transistor with thin gate oxide and low gate charge	Electricity	6	Active
US8946851B1	Integrated MOS power transistor with thin gate oxide and low gate charge	Electricity	5	Active
US9502251B1	Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process	Electricity	5	Active
US9941171B1	Method for fabricating LDMOS with reduced source region	Electricity	3	Active
US10665712B2	LDMOS device with a field plate contact metal layer with a sub-maximum size	Electricity	2	Active
US9450052B1	EEPROM memory cell with a coupler region and method of making the same	Electricity	2	Active
US9087774B2	LDMOS device with short channel and associated fabrication method	Electricity	2	Active
US9041102B2	Power transistor and associated method for manufacturing	Electricity	1	Active
US9893170B1	Manufacturing method of selectively etched DMOS body pickup	Electricity	1	Active
US9893146B1	Lateral DMOS and the method for forming thereof	Electricity	1	Active
US11069777B1	Manufacturing method of self-aligned DMOS body pickup	Electricity	0	Active
US11508806B1	Low leakage ESD MOSFET	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.