Packages and methods for 3D integration including two stacked dies with a portion of one die extending into a hole of the other die
US8946879B2 · kind B2 · utility
5Cited by
7References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Jan 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packages and methods for 3D integration are disclosed. In various embodiments, a first integrated device die having a hole is attached to a package substrate. A second integrated device die can be stacked on top of the first integrated device die. At least a portion of the second integrated device die can extend into the hole of the first integrated device die. By stacking the two dies such that the portion of the second integrated device die extends into the hole, the overall package height can advantageously be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.