Semiconductor device, manufacturing method of semiconductor device, semiconductor manufacturing and inspecting apparatus, and inspecting apparatus
US8946895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2009 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Dec 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.