Enhanced immunity from electrostatic discharge
US8947839B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2009 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Oct 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.