Stable SRAM cell
US8947900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2014 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | May 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.