Patent · US Active

Memory having power saving mode

US8947968B2 · kind B2 · utility

5Cited by

0References

11Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Wang-Kun Chen · Austin, US
Yew Keong Chong · Austin, US
Sriram Thyagarajan · Austin, US
Gus Yeung · Austin, US

Key dates

Filing date	Jul 8, 2013
Grant date	Feb 3, 2015
Priority date	—
Expiry date	Jul 8, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.