Just in time compiler in spatially aware emulation of a guest computer instruction set
US8949106B2 · kind B2 · utility
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26References
18Claims
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Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Oct 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.