Circuit for forward error correction encoding of data blocks across multiple data lanes
US8949699B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2012 |
| Grant date | Feb 3, 2015 |
| Priority date | — |
| Expiry date | Mar 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for communicating a sequence of data bits is provided. FEC coding is performed on a received sequence of data bits to produce an FEC coded sequence formatted for a first set of N data lanes. The FEC coded sequence includes FEC data blocks, in which each FEC data block has a plurality of data symbols. Alignment markers are added to the FEC coded sequence and the FEC coded sequence is multiplexed to produce a multiplexed sequence formatted for a second set of M data lanes. The multiplexing is performed only at boundaries between the data symbols or the alignment markers. The multiplexed sequence is transmitted on M data lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.