Defect free deep trench method for semiconductor chip
US8951833B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2011 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | May 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.