Semiconductor device having decoupling capacitors and dummy transistors
US8952423B2 · kind B2 · utility
6Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/66
Abstract
A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.