Electrostatic discharge protection circuit
US8952457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Apr 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.