Electronic circuit arrangement

US8952487B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Hans-Joachim Barth · Munich, DE
• Andreas Rusch · Dresden, DE
• Klaus Schruefer · Baldham, DE

Key dates

• Filing date: Feb 25, 2014
• Grant date: Feb 10, 2015
• Expiry date: Feb 25, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.