Scribe lines in wafers
US8952497B2 · kind B2 · utility
5Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Sep 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.