Chip package and fabrication method thereof
US8952519B2 · kind B2 · utility
6Cited by
3References
18Claims
0Family size
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Feb 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1579
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.