Systems, methods, and apparatus for memory cells with common source lines
US8953380B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2014 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jun 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.