Block level grading for reliability and yield improvement
US8953398B2 · kind B2 · utility
5Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2012 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.