Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
US8954017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2011 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.