Memory address translation-based data encryption with integrated encryption engine
US8954755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2012 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Jul 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit arrangement utilize an integrated encryption engine within a processing core of a multi-core processor to perform encryption operations, i.e., encryption and decryption of secure data, in connection with memory access requests that access such data. The integrated encryption engine is utilized in combination with a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB) that is augmented with encryption-related page attributes to indicate whether pages of memory identified in the data structure are encrypted such that secure data associated with a memory access request in the processing core may be selectively streamed to the integrated encryption engine based upon the encryption-related page attribute for the memory page associated with the memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.