Analyze and reduce number of data reordering operations in SIMD code
US8954943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2006 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing data reordering operations in Single Issue Multiple Data source code and generating executable code therefrom is provided. Input is received. One or more data reordering operations in the input are identified and each data reordering operation in the input is abstracted into a corresponding virtual shuffle operation so that each virtual shuffle operation forms part of an expression tree. One or more virtual shuffle trees are collapsed by combining virtual shuffle operations within at least one of the one or more virtual shuffle trees to form one or more combined virtual shuffle operations, wherein each virtual shuffle tree is a subtree of the expression tree that only contains virtual shuffle operations. Then code is generated for the one or more combined virtual shuffle operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.