3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US8957525B2 · kind B2 · utility
24Cited by
1References
13Claims
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Key dates
| Filing date | Dec 6, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Mar 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (TSVs), while the chips are free of TSVs. The TSVs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110). Symmetrically positioned relative to interposer (120), and connected to it by short signal traces, chips (130, 140) are attached to the TSVs of interposer 110, which in turn is attached to a substrate (160) with supply connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.