Wafer level package resistance monitor scheme
US8957694B2 · kind B2 · utility
7Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2012 |
| Grant date | Feb 17, 2015 |
| Priority date | — |
| Expiry date | Mar 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.